616 lines
18 KiB
C
616 lines
18 KiB
C
/*
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* Portions of this file taken from the Linux kernel,
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* Copyright 1991-2009 Linus Torvalds and contributors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdio.h>
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#include <string.h>
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#include "cpuid.h"
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const char *cpu_flags_names[] = {
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CPU_FLAGS(STRUCT_MEMBER_NAMES)
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};
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size_t cpu_flags_offset[] = {
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CPU_FLAGS(STRUCTURE_MEMBER_OFFSETS)
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};
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size_t cpu_flags_count = sizeof cpu_flags_names / sizeof *cpu_flags_names;
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struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = { };
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bool get_cpu_flag_value_from_name(s_cpu *cpu, const char * flag_name) {
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size_t i;
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bool cpu_flag_present=false, *flag_value = &cpu_flag_present;
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for (i = 0; i < cpu_flags_count; i++) {
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if (strcmp(cpu_flags_names[i],flag_name) == 0) {
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flag_value = (bool *)((char *)&cpu->flags + cpu_flags_offset[i]);
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}
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}
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return *flag_value;
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}
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/*
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* CPUID functions returning a single datum
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*/
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/* Probe for the CPUID instruction */
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static int have_cpuid_p(void)
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{
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return cpu_has_eflag(X86_EFLAGS_ID);
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}
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static struct cpu_dev amd_cpu_dev = {
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.c_vendor = "AMD",
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.c_ident = {"AuthenticAMD"}
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};
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static struct cpu_dev intel_cpu_dev = {
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.c_vendor = "Intel",
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.c_ident = {"GenuineIntel"}
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};
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static struct cpu_dev cyrix_cpu_dev = {
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.c_vendor = "Cyrix",
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.c_ident = {"CyrixInstead"}
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};
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static struct cpu_dev umc_cpu_dev = {
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.c_vendor = "UMC",
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.c_ident = {"UMC UMC UMC"}
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};
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static struct cpu_dev nexgen_cpu_dev = {
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.c_vendor = "Nexgen",
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.c_ident = {"NexGenDriven"}
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};
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static struct cpu_dev centaur_cpu_dev = {
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.c_vendor = "Centaur",
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.c_ident = {"CentaurHauls"}
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};
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static struct cpu_dev rise_cpu_dev = {
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.c_vendor = "Rise",
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.c_ident = {"RiseRiseRise"}
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};
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static struct cpu_dev transmeta_cpu_dev = {
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.c_vendor = "Transmeta",
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.c_ident = {"GenuineTMx86", "TransmetaCPU"}
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};
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static struct cpu_dev nsc_cpu_dev = {
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.c_vendor = "National Semiconductor",
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.c_ident = {"Geode by NSC"}
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};
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static struct cpu_dev unknown_cpu_dev = {
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.c_vendor = "Unknown Vendor",
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.c_ident = {"Unknown CPU"}
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};
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/*
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* Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
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*/
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void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
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{
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unsigned char ccr2, ccr3;
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/* we test for DEVID by checking whether CCR3 is writable */
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ccr3 = getCx86(CX86_CCR3);
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setCx86(CX86_CCR3, ccr3 ^ 0x80);
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getCx86(0xc0); /* dummy to change bus */
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if (getCx86(CX86_CCR3) == ccr3) { /* no DEVID regs. */
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ccr2 = getCx86(CX86_CCR2);
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setCx86(CX86_CCR2, ccr2 ^ 0x04);
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getCx86(0xc0); /* dummy */
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if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
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*dir0 = 0xfd;
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else { /* Cx486S A step */
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setCx86(CX86_CCR2, ccr2);
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*dir0 = 0xfe;
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}
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} else {
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setCx86(CX86_CCR3, ccr3); /* restore CCR3 */
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/* read DIR0 and DIR1 CPU registers */
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*dir0 = getCx86(CX86_DIR0);
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*dir1 = getCx86(CX86_DIR1);
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}
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}
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void init_cpu_devs(void)
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{
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cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
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cpu_devs[X86_VENDOR_CYRIX] = &cyrix_cpu_dev;
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cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
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cpu_devs[X86_VENDOR_UMC] = &umc_cpu_dev;
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cpu_devs[X86_VENDOR_NEXGEN] = &nexgen_cpu_dev;
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cpu_devs[X86_VENDOR_CENTAUR] = ¢aur_cpu_dev;
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cpu_devs[X86_VENDOR_RISE] = &rise_cpu_dev;
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cpu_devs[X86_VENDOR_TRANSMETA] = &transmeta_cpu_dev;
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cpu_devs[X86_VENDOR_NSC] = &nsc_cpu_dev;
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cpu_devs[X86_VENDOR_UNKNOWN] = &unknown_cpu_dev;
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}
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void get_cpu_vendor(struct cpuinfo_x86 *c)
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{
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char *v = c->x86_vendor_id;
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int i;
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init_cpu_devs();
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for (i = 0; i < X86_VENDOR_NUM-1; i++) {
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if (cpu_devs[i]) {
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if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
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(cpu_devs[i]->c_ident[1] &&
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!strcmp(v, cpu_devs[i]->c_ident[1]))) {
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c->x86_vendor = i;
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return;
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}
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}
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}
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c->x86_vendor = X86_VENDOR_UNKNOWN;
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}
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int get_model_name(struct cpuinfo_x86 *c)
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{
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unsigned int *v;
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char *p, *q;
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if (cpuid_eax(0x80000000) < 0x80000004)
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return 0;
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v = (unsigned int *)c->x86_model_id;
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cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
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cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
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cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
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c->x86_model_id[48] = 0;
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/* Intel chips right-justify this string for some dumb reason;
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undo that brain damage */
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p = q = &c->x86_model_id[0];
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while (*p == ' ')
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p++;
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if (p != q) {
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while (*p)
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*q++ = *p++;
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while (q <= &c->x86_model_id[48])
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*q++ = '\0'; /* Zero-pad the rest */
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}
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return 1;
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}
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void detect_cache(uint32_t xlvl, struct cpuinfo_x86 *c)
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{
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uint32_t eax, ebx, ecx, edx, l2size;
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/* Detecting L1 cache */
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if (xlvl >= 0x80000005) {
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cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
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c->x86_l1_data_cache_size = ecx >> 24;
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c->x86_l1_instruction_cache_size = edx >> 24;
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}
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/* Detecting L2 cache */
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c->x86_l2_cache_size = 0;
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if (xlvl < 0x80000006) /* Some chips just has a large L1. */
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return;
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cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
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l2size = ecx >> 16;
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/* Vendor based fixes */
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switch (c->x86_vendor) {
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case X86_VENDOR_INTEL:
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/*
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* Intel PIII Tualatin. This comes in two flavours.
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* One has 256kb of cache, the other 512. We have no way
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* to determine which, so we use a boottime override
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* for the 512kb model, and assume 256 otherwise.
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*/
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if ((c->x86 == 6) && (c->x86_model == 11) && (l2size == 0))
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l2size = 256;
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break;
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case X86_VENDOR_AMD:
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/* AMD errata T13 (order #21922) */
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if ((c->x86 == 6)) {
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if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
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l2size = 64;
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if (c->x86_model == 4 && (c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */
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l2size = 256;
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}
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break;
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}
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c->x86_l2_cache_size = l2size;
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}
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void detect_cyrix(struct cpuinfo_x86 *c) {
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unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
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char *buf = c->x86_model_id;
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char Cx86_cb[] = "?.5x Core/Bus Clock";
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const char cyrix_model_mult1[] = "12??43";
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const char cyrix_model_mult2[] = "12233445";
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const char *p = NULL;
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do_cyrix_devid(&dir0, &dir1);
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dir0_msn = dir0 >> 4; /* identifies CPU "family" */
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dir0_lsn = dir0 & 0xf; /* model or clock multiplier */
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c->x86_model = (dir1 >> 4) + 1;
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c->x86_mask = dir1 & 0xf;
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switch (dir0_msn) {
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unsigned char tmp;
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case 0: /* Cx486SLC/DLC/SRx/DRx */
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p = Cx486_name[dir0_lsn & 7];
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break;
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case 1: /* Cx486S/DX/DX2/DX4 */
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p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5] : Cx486S_name[dir0_lsn & 3];
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break;
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case 2: /* 5x86 */
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Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
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p = Cx86_cb+2;
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break;
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case 3: /* 6x86/6x86L */
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Cx86_cb[1] = ' ';
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Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
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if (dir1 > 0x21) { /* 686L */
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Cx86_cb[0] = 'L';
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p = Cx86_cb;
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(c->x86_model)++;
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} else /* 686 */
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p = Cx86_cb+1;
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c->coma_bug = 1;
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break;
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case 4:
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c->x86_l1_data_cache_size = 16; /* Yep 16K integrated cache thats it */
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if (c->cpuid_level != 2) { /* Media GX */
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Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
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p = Cx86_cb+2;
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}
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break;
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case 5: /* 6x86MX/M II */
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if (dir1 > 7) {
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dir0_msn++; /* M II */
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} else {
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c->coma_bug = 1; /* 6x86MX, it has the bug. */
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}
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tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
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Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
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p = Cx86_cb+tmp;
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if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
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(c->x86_model)++;
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break;
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case 0xf: /* Cyrix 486 without DEVID registers */
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switch (dir0_lsn) {
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case 0xd: /* either a 486SLC or DLC w/o DEVID */
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dir0_msn = 0;
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p = Cx486_name[(c->hard_math) ? 1 : 0];
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break;
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case 0xe: /* a 486S A step */
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dir0_msn = 0;
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p = Cx486S_name[0];
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break;
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}
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break;
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default:
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dir0_msn = 7;
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break;
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}
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/* If the processor is unknown, we keep the model name we got
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* from the generic call */
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if (dir0_msn < 7) {
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strcpy(buf, Cx86_model[dir0_msn & 7]);
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if (p) strcat(buf, p);
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}
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}
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void generic_identify(struct cpuinfo_x86 *c)
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{
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uint32_t tfms, xlvl;
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uint32_t eax, ebx, ecx, edx;
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/* Get vendor name */
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cpuid(0x00000000,
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(uint32_t *) & c->cpuid_level,
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(uint32_t *) & c->x86_vendor_id[0],
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(uint32_t *) & c->x86_vendor_id[8],
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(uint32_t *) & c->x86_vendor_id[4]);
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get_cpu_vendor(c);
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/* Intel-defined flags: level 0x00000001 */
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if (c->cpuid_level >= 0x00000001) {
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uint32_t capability, excap;
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cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
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c->x86_capability[0] = capability;
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c->x86_capability[4] = excap;
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c->x86 = (tfms >> 8) & 15;
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c->x86_model = (tfms >> 4) & 15;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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c->x86_mask = tfms & 15;
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if (cpu_has(c, X86_FEATURE_CLFLSH))
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c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
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} else {
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/* Have CPUID level 0 only - unheard of */
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c->x86 = 4;
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}
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/* AMD-defined flags: level 0x80000001 */
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xlvl = cpuid_eax(0x80000000);
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if ((xlvl & 0xffff0000) == 0x80000000) {
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if (xlvl >= 0x80000001) {
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c->x86_capability[1] = cpuid_edx(0x80000001);
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c->x86_capability[6] = cpuid_ecx(0x80000001);
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}
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if (xlvl >= 0x80000004)
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get_model_name(c); /* Default name */
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}
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/* Specific detection code */
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switch (c->x86_vendor) {
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case X86_VENDOR_CYRIX:
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case X86_VENDOR_NSC: detect_cyrix(c); break;
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default: break;
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}
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/* Detecting the number of cores */
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switch (c->x86_vendor) {
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case X86_VENDOR_AMD:
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if (xlvl >= 0x80000008) {
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c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
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if (c->x86_num_cores & (c->x86_num_cores - 1))
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c->x86_num_cores = 1;
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}
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break;
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case X86_VENDOR_INTEL:
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if (c->cpuid_level >= 0x00000004) {
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cpuid(0x4, &eax, &ebx, &ecx, &edx);
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c->x86_num_cores = ((eax & 0xfc000000) >> 26) + 1;
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}
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break;
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default:
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c->x86_num_cores = 1;
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break;
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}
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detect_cache(xlvl, c);
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}
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/*
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* Checksum an MP configuration block.
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*/
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static int mpf_checksum(unsigned char *mp, int len)
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{
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int sum = 0;
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while (len--)
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sum += *mp++;
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return sum & 0xFF;
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}
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static int smp_scan_config(unsigned long base, unsigned long length)
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{
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unsigned long *bp = (unsigned long *)base;
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struct intel_mp_floating *mpf;
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// printf("Scan SMP from %p for %ld bytes.\n", bp,length);
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if (sizeof(*mpf) != 16) {
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printf("Error: MPF size\n");
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return 0;
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}
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while (length > 0) {
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mpf = (struct intel_mp_floating *)bp;
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if ((*bp == SMP_MAGIC_IDENT) &&
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(mpf->mpf_length == 1) &&
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!mpf_checksum((unsigned char *)bp, 16) &&
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((mpf->mpf_specification == 1)
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|| (mpf->mpf_specification == 4))) {
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return 1;
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}
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bp += 4;
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length -= 16;
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}
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return 0;
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}
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int find_smp_config(void)
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{
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// unsigned int address;
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/*
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* FIXME: Linux assumes you have 640K of base ram..
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* this continues the error...
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*
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* 1) Scan the bottom 1K for a signature
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* 2) Scan the top 1K of base RAM
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* 3) Scan the 64K of bios
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*/
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if (smp_scan_config(0x0, 0x400) ||
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smp_scan_config(639 * 0x400, 0x400) ||
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smp_scan_config(0xF0000, 0x10000))
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return 1;
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/*
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* If it is an SMP machine we should know now, unless the
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* configuration is in an EISA/MCA bus machine with an
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* extended bios data area.
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*
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* there is a real-mode segmented pointer pointing to the
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* 4K EBDA area at 0x40E, calculate and scan it here.
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*
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* NOTE! There are Linux loaders that will corrupt the EBDA
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* area, and as such this kind of SMP config may be less
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* trustworthy, simply because the SMP table may have been
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* stomped on during early boot. These loaders are buggy and
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* should be fixed.
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*
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* MP1.4 SPEC states to only scan first 1K of 4K EBDA.
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*/
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// address = get_bios_ebda();
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// if (address)
|
|
// smp_scan_config(address, 0x400);
|
|
return 0;
|
|
}
|
|
|
|
void set_cpu_flags(struct cpuinfo_x86 *c, s_cpu * cpu)
|
|
{
|
|
cpu->flags.fpu = cpu_has(c, X86_FEATURE_FPU);
|
|
cpu->flags.vme = cpu_has(c, X86_FEATURE_VME);
|
|
cpu->flags.de = cpu_has(c, X86_FEATURE_DE);
|
|
cpu->flags.pse = cpu_has(c, X86_FEATURE_PSE);
|
|
cpu->flags.tsc = cpu_has(c, X86_FEATURE_TSC);
|
|
cpu->flags.msr = cpu_has(c, X86_FEATURE_MSR);
|
|
cpu->flags.pae = cpu_has(c, X86_FEATURE_PAE);
|
|
cpu->flags.mce = cpu_has(c, X86_FEATURE_MCE);
|
|
cpu->flags.cx8 = cpu_has(c, X86_FEATURE_CX8);
|
|
cpu->flags.apic = cpu_has(c, X86_FEATURE_APIC);
|
|
cpu->flags.sep = cpu_has(c, X86_FEATURE_SEP);
|
|
cpu->flags.mtrr = cpu_has(c, X86_FEATURE_MTRR);
|
|
cpu->flags.pge = cpu_has(c, X86_FEATURE_PGE);
|
|
cpu->flags.mca = cpu_has(c, X86_FEATURE_MCA);
|
|
cpu->flags.cmov = cpu_has(c, X86_FEATURE_CMOV);
|
|
cpu->flags.pat = cpu_has(c, X86_FEATURE_PAT);
|
|
cpu->flags.pse_36 = cpu_has(c, X86_FEATURE_PSE36);
|
|
cpu->flags.psn = cpu_has(c, X86_FEATURE_PN);
|
|
cpu->flags.clflsh = cpu_has(c, X86_FEATURE_CLFLSH);
|
|
cpu->flags.dts = cpu_has(c, X86_FEATURE_DTES);
|
|
cpu->flags.acpi = cpu_has(c, X86_FEATURE_ACPI);
|
|
cpu->flags.pbe = cpu_has(c, X86_FEATURE_PBE);
|
|
cpu->flags.mmx = cpu_has(c, X86_FEATURE_MMX);
|
|
cpu->flags.fxsr = cpu_has(c, X86_FEATURE_FXSR);
|
|
cpu->flags.sse = cpu_has(c, X86_FEATURE_XMM);
|
|
cpu->flags.sse2 = cpu_has(c, X86_FEATURE_XMM2);
|
|
cpu->flags.ss = cpu_has(c, X86_FEATURE_SELFSNOOP);
|
|
cpu->flags.htt = cpu_has(c, X86_FEATURE_HT);
|
|
cpu->flags.acc = cpu_has(c, X86_FEATURE_ACC);
|
|
cpu->flags.syscall = cpu_has(c, X86_FEATURE_SYSCALL);
|
|
cpu->flags.mp = cpu_has(c, X86_FEATURE_MP);
|
|
cpu->flags.nx = cpu_has(c, X86_FEATURE_NX);
|
|
cpu->flags.mmxext = cpu_has(c, X86_FEATURE_MMXEXT);
|
|
cpu->flags.fxsr_opt = cpu_has(c, X86_FEATURE_FXSR_OPT);
|
|
cpu->flags.gbpages = cpu_has(c, X86_FEATURE_GBPAGES);
|
|
cpu->flags.rdtscp = cpu_has(c, X86_FEATURE_RDTSCP);
|
|
cpu->flags.lm = cpu_has(c, X86_FEATURE_LM);
|
|
cpu->flags.nowext = cpu_has(c, X86_FEATURE_3DNOWEXT);
|
|
cpu->flags.now = cpu_has(c, X86_FEATURE_3DNOW);
|
|
cpu->flags.smp = find_smp_config();
|
|
cpu->flags.pni = cpu_has(c, X86_FEATURE_XMM3);
|
|
cpu->flags.pclmulqd = cpu_has(c, X86_FEATURE_PCLMULQDQ);
|
|
cpu->flags.dtes64 = cpu_has(c, X86_FEATURE_DTES64);
|
|
cpu->flags.vmx = cpu_has(c, X86_FEATURE_VMX);
|
|
cpu->flags.smx = cpu_has(c, X86_FEATURE_SMX);
|
|
cpu->flags.est = cpu_has(c, X86_FEATURE_EST);
|
|
cpu->flags.tm2 = cpu_has(c, X86_FEATURE_TM2);
|
|
cpu->flags.sse3 = cpu_has(c, X86_FEATURE_SSE3);
|
|
cpu->flags.cid = cpu_has(c, X86_FEATURE_CID);
|
|
cpu->flags.fma = cpu_has(c, X86_FEATURE_FMA);
|
|
cpu->flags.cx16 = cpu_has(c, X86_FEATURE_CX16);
|
|
cpu->flags.xtpr = cpu_has(c, X86_FEATURE_XTPR);
|
|
cpu->flags.pdcm = cpu_has(c, X86_FEATURE_PDCM);
|
|
cpu->flags.dca = cpu_has(c, X86_FEATURE_DCA);
|
|
cpu->flags.xmm4_1 = cpu_has(c, X86_FEATURE_XMM4_1);
|
|
cpu->flags.xmm4_2 = cpu_has(c, X86_FEATURE_XMM4_2);
|
|
cpu->flags.x2apic = cpu_has(c, X86_FEATURE_X2APIC);
|
|
cpu->flags.movbe = cpu_has(c, X86_FEATURE_MOVBE);
|
|
cpu->flags.popcnt = cpu_has(c, X86_FEATURE_POPCNT);
|
|
cpu->flags.aes = cpu_has(c, X86_FEATURE_AES);
|
|
cpu->flags.xsave = cpu_has(c, X86_FEATURE_XSAVE);
|
|
cpu->flags.osxsave = cpu_has(c, X86_FEATURE_OSXSAVE);
|
|
cpu->flags.avx = cpu_has(c, X86_FEATURE_AVX);
|
|
cpu->flags.hypervisor = cpu_has(c, X86_FEATURE_HYPERVISOR);
|
|
cpu->flags.ace2 = cpu_has(c, X86_FEATURE_ACE2);
|
|
cpu->flags.ace2_en = cpu_has(c, X86_FEATURE_ACE2_EN);
|
|
cpu->flags.phe = cpu_has(c, X86_FEATURE_PHE);
|
|
cpu->flags.phe_en = cpu_has(c, X86_FEATURE_PHE_EN);
|
|
cpu->flags.pmm = cpu_has(c, X86_FEATURE_PMM);
|
|
cpu->flags.pmm_en = cpu_has(c, X86_FEATURE_PMM_EN);
|
|
cpu->flags.extapic = cpu_has(c, X86_FEATURE_EXTAPIC);
|
|
cpu->flags.cr8_legacy = cpu_has(c, X86_FEATURE_CR8_LEGACY);
|
|
cpu->flags.abm = cpu_has(c, X86_FEATURE_ABM);
|
|
cpu->flags.sse4a = cpu_has(c, X86_FEATURE_SSE4A);
|
|
cpu->flags.misalignsse = cpu_has(c, X86_FEATURE_MISALIGNSSE);
|
|
cpu->flags.nowprefetch = cpu_has(c, X86_FEATURE_3DNOWPREFETCH);
|
|
cpu->flags.osvw = cpu_has(c, X86_FEATURE_OSVW);
|
|
cpu->flags.ibs = cpu_has(c, X86_FEATURE_IBS);
|
|
cpu->flags.sse5 = cpu_has(c, X86_FEATURE_SSE5);
|
|
cpu->flags.skinit = cpu_has(c, X86_FEATURE_SKINIT);
|
|
cpu->flags.wdt = cpu_has(c, X86_FEATURE_WDT);
|
|
cpu->flags.ida = cpu_has(c, X86_FEATURE_IDA);
|
|
cpu->flags.arat = cpu_has(c, X86_FEATURE_ARAT);
|
|
cpu->flags.tpr_shadow = cpu_has(c, X86_FEATURE_TPR_SHADOW);
|
|
cpu->flags.vnmi = cpu_has(c, X86_FEATURE_VNMI);
|
|
cpu->flags.flexpriority = cpu_has(c, X86_FEATURE_FLEXPRIORITY);
|
|
cpu->flags.ept = cpu_has(c, X86_FEATURE_EPT);
|
|
cpu->flags.vpid = cpu_has(c, X86_FEATURE_VPID);
|
|
cpu->flags.svm = cpu_has(c, X86_FEATURE_SVM);
|
|
}
|
|
|
|
void set_generic_info(struct cpuinfo_x86 *c, s_cpu * cpu)
|
|
{
|
|
cpu->family = c->x86;
|
|
cpu->vendor_id = c->x86_vendor;
|
|
cpu->model_id = c->x86_model;
|
|
cpu->stepping = c->x86_mask;
|
|
strlcpy(cpu->vendor, cpu_devs[c->x86_vendor]->c_vendor,
|
|
sizeof(cpu->vendor));
|
|
strlcpy(cpu->model, c->x86_model_id, sizeof(cpu->model));
|
|
cpu->num_cores = c->x86_num_cores;
|
|
cpu->l1_data_cache_size = c->x86_l1_data_cache_size;
|
|
cpu->l1_instruction_cache_size = c->x86_l1_instruction_cache_size;
|
|
cpu->l2_cache_size = c->x86_l2_cache_size;
|
|
}
|
|
|
|
void detect_cpu(s_cpu * cpu)
|
|
{
|
|
struct cpuinfo_x86 c;
|
|
memset(&c,0,sizeof(c));
|
|
c.x86_clflush_size = 32;
|
|
c.x86_vendor = X86_VENDOR_UNKNOWN;
|
|
c.cpuid_level = -1; /* CPUID not detected */
|
|
c.x86_num_cores = 1;
|
|
memset(&cpu->flags, 0, sizeof(s_cpu_flags));
|
|
|
|
if (!have_cpuid_p())
|
|
return;
|
|
|
|
generic_identify(&c);
|
|
set_generic_info(&c, cpu);
|
|
set_cpu_flags(&c, cpu);
|
|
}
|